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rev. 0.2 11/10 copyright ? 2010 by silicon laboratories si5350c this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5350c f actory -p rogrammable a ny -f requency cmos c lock g enerator + pll features applications description the si5350c generates free-running and/or synchronized clocks selectable on each of its outputs. a dual pll + high resolution multisynth tm fractional divider architecture enables this user-definabl e custom timing device to generate any of the specified output frequencies at any of its outputs. this allows the si5350c to replace a combination of crystals, crystal oscillators, and synchronized clocks (pll). custom pin-controlled si5350c devices are requested using the clockbuilder web-based part number utility ( www.silabs.com/clockbuilder ). ? generates up to 8 non-integer frequencies from 8 khz to 125 mhz ? exact frequency synthesis at each output (0 ppm error) ? glitchless frequency changes ? low output period jitter: 100 ps pp ? configurable spread spectrum selectable at each output ? user-configurable control pins: ?? output enable (oeb_0/1/2) ?? power down (pdn) ?? frequency select (fs_0/1) ?? spread spectrum enable (ssen) ?? loss of lock status (lol) ? operates from a low-cost, fixed frequency crystal: 25 or 27 mhz ? separate voltage supply pins: ?? core vdd: 2.5 v or 3.3 v ?? output vddo: 2.5 v or 3.3 v ? excellent psrr eliminates external power supply filtering ? very low power consumption (<15 ma) ? available in 3 packages types: ?? 10-msop: 3 outputs ?? 24-qsop: 8 outputs ?? 20-qfn (4x4 mm): 8 outputs ? hdtv, dvd/blu-ray, set-top box ? audio/video equipment, gaming ? printers, scanners, projectors ? residential gateways ? networking/communication ? servers, storage ordering information: see page 20 20-qfn 24-qsop 10-msop clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 multi synth 0 multi synth 1 multi synth 2 multi synth 3 multi synth 4 multi synth 5 multi synth 6 multi synth 7 p0 p1 p2 p3 control logic osc xa xb clkin plla pllb 20-qfn, 24-qsop si5350c clk0 clk1 clk2 p0 control logic multi synth 0 multi synth 1 multi synth 2 osc xa xb clkin plla pllb si5350c 10-msop
si5350c 2 rev. 0.2
si5350c rev. 0.2 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. configuring the si5350c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1. crystal inputs (xa, xb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2. external clock input pin (clkin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3. output clocks (clk0?clk7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4. programmable control pi ns (p0?p3) options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. pin descriptions (20-qfn, 24-qsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6. pin descriptions (10-msop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. package outline (24-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8. package outline (20-pin qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1. package outline (10-pin msop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
si5350c 4 rev. 0.2 1. electrical specifications table 1. recommended operating conditions (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit ambient temperature t a ?40 25 85 c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v output buffer voltage v ddox 2.97 3.3 3.63 v 2.25 2.5 2.75 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. table 2. absolute maximum ratings parameter symbol test condition value unit dc supply voltage v dd_max ?0.5 to 3.8 v input voltage vin_p1-3 pins p1, p2, p3 ?0.5 to 3.8 v vin_p0 p0 ?0.5 to (vdd+0.3) v vin_xa/b pins xa, xb ?0.5 to 1.3 v v storage temperature range tstg ?55 to 150 c operating junction temperature t jct ?55 to 150 c note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3. dc characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit core supply current i dd enabled 3 outputs ? 20 26 ma enabled 8 outputs ? 25 38 ma power down (pdn = v dd )? 50 ? a output buffer supply current i ddox c l =5pf ? 2.5 4 ma input current i p1-p3 pins p1, p2, p3 vin<3.6v ??10 a i p0 pin p0 ? ? 30 a
si5350c rev. 0.2 5 table 4. ac characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit power-up time t rdy from v dd =v ddmin to valid output clock, c l =15pf, f clkn > 1 mhz ?110ms output enable time t oe from oeb assertion to valid clock output, c l = 15 pf, f clkn > 1 mhz ??10s output frequency transition time t freq time to settle to within 20 ppm of specified frequency upon change in frequency plan via fs pin, f clkn >1mhz ? 100 ? s minimum pulse width t pw_pdn power down pin (pdn) 100 ? ? ms t pw_p0-3 control pin (p0?p3) 200 ? ? ns spread spectrum frequency deviation ss dev down spread ?0.5 ? ?2.5 % spread spectrum modulation rate ss mod_c 30 31.5 33 khz table 5. thermal characteristics parameter symbol test cond ition package value unit thermal resistance junction to ambient ? ja still air 10-msop 131 c/w 24-qsop 80 c/w 20-qfn 51 c/w thermal resistance junction to case ? jc still air 10-msop 43 c/w 24-qsop 31 c/w 20-qfn 16 c/w
si5350c 6 rev. 0.2 table 6. input characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units crystal frequency f xtal 25 ? 27 mhz p0-p3 input low voltage v il_p0-3 ?0.1 ? 0.3 x v dd v p0-p3 input high voltage v ih_p0-3 0.7 x v dd ?3.63v clkin frequency range f clkin 10 ? 100 mhz clkin input low voltage v il_clkin ?0.1 ? 0.3 x v dd v clkin input high voltage v ih_clkin 0.7 x v dd ?3.63v table 7. output characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units frequency range f clk 0.008 ? 133 mhz load capacitance c l f clk < 100 mhz ? ? 15 pf duty cycle dc measured at v dd /2 45 50 55 % rise/fall time t r /t f 20%?80%, c l = 5 pf 0.6 1 1.3 ns output high voltage v oh c l =5pf v dd ? 0.6 ? ? v output low voltage v ol ??0.6v period jitter j per measured over 10k cycles ? 35 100 ps pk-pk cycle-to-cycle jitter j cc measured over 10k cycles ? 30 90 ps pk-pk rms jitter j rms 12 khz?20 mhz ? 3.5 11 ps
si5350c rev. 0.2 7 table 8. 25 mhz crystal requirements 1,2 parameter symbol min typ max unit crystal frequency f xtal ?25?mhz load capacitance c l 6?12pf equivalent series resistance r esr ??150 ? crystal max drive level d l ??100w notes: 1. crystals which require load capacitances of 6, 8, or 10 pf should use the device?s internal load capacitance for optimum performance. see register 183 bits 7:6. a crystal with a 12 pf lo ad capacitance requirement should use a combination of the internal 10 pf load capacitors in addition to external 2 pf load capacitors. 2. refer to ?an551: crystal selection guide? for more details. table 9. 27 mhz crystal requirements 1,2 parameter symbol min typ max unit crystal frequency f xtal ?27?mhz load capacitance c l 6?12pf equivalent series resistance r esr ??150 ? crystal max drive level d l ??100w notes: 1. crystals which require load capacitances of 6, 8, or 10 pf should use the device?s internal load capacitance for optimum performance. see register 183 bits 7:6. a crystal with a 12 pf lo ad capacitance requirement should use a combination of the internal 10 pf load capacitors in addition to external 2 pf load capacitors. 2. refer to ?an551: crystal selection guide? for more details.
si5350c 8 rev. 0.2 2. typical application the si5350c is a clock genera tion device that provides both synchron ous and free-running clocks for applications where power, board size, and cost are critical. an example application is shown in figure 1. any other combination is possible. figure 1. replacing multiple xtal/xos and plls with one si5350c ethernet phy usb controller hdmi port 28.322 mhz 48 mhz 125 mhz video/audio processor 74.25/1.001 mhz 24.576 mhz osc xa xb clk0 clk1 clk2 clk3 clk4 clk5 pll pll multi synth 0 multi synth 1 multi synth 2 74.25 mhz clkin 27 mhz si5350c multi synth 3 multi synth 4 multi synth 5 54 mhz free-running clocks synchronous clocks
si5350c rev. 0.2 9 3. functional description the architecture of the si5350c generat es of up to eight non-integer-related frequencies in any combination of free-running and/or synchronous clocks. a block diagram of both the 3-output and the 8-output versions are shown in figure 2. free-running clocks are ge nerated using the on-chip oscillator + pll, and the clock input pin (clkin) provides an external input reference fo r the synchronous cloc ks. each multisynth tm is configurable with two frequencies (f1_x, f2_x). this allows a pin controlled glit chless frequency change at each output (clk0 to clk5). figure 2. block diagrams of the si5350c devices with 3 and 8 outputs 10-msop multisynth 3 f1_2 f2_2 r2 fs multisynth 2 vdd gnd clk2 f1_0 f2_0 r0 fs multisynth 0 f1_1 f2_1 r1 fs multisynth 1 clk0 clk1 vddo f1_3 f2_3 r3 fs multisynth 3 f1_2 f2_2 r2 fs multisynth 2 20-qfn, 24-qsop vdd gnd clk2 clk3 vddob control logic p2 p3 p0 p1 f1_0 f2_0 r0 fs multisynth 0 f1_1 f2_1 r1 fs multisynth 1 clk0 clk1 vddoa r6 r7 clk6 clk7 vddod f1_4 f2_4 r4 fs multisynth 4 f1_5 f2_5 r5 fs multisynth 5 clk4 clk5 vddoc f1_6 multisynth 6 f1_7 multisynth 7 control logic p0 pll a osc xa xb clkin pll a osc xa xb clkin pll b pll b
si5350c 10 rev. 0.2 4. configuring the si5350c the si5350c is a factory-programmed custom clock generato r that is user definable with a simple to use web- based utility ( www.silabs.com/clockbuilder ). the clockbuilder utility provides a simple graphica l interface that allows the user to enter input and output frequencies alon g with other custom features as described in the following sections. all synthesis calculations are automatica lly performed by clockbuilder to ensure an optimum configuration. a unique part number is assigned to ea ch custom configuration. samples of any custom si5350c factory-programmed clock generator are available with short lead times. 4.1. crystal inputs (xa, xb) the si5350c uses an optional fixed-frequency non-pullabl e standard at-cut crystal as a reference to generate free-running output clocks. note that a xtal is not required for generating synchronous clocks that are locked to clkin. 4.1.1. crystal frequency the si5350c can operate using either a 25 mhz or a 27 mhz crystal. 4.1.2. internal xtal load capacitors internal load capacitors (c l ) are provided to eliminate the need for external components when connecting a xtal to the si5350c. options for internal load capacitors are 6, 8, or 10 pf, or no internal load capacitors. xtals with alternate load capacitance requirements are supported using external load capacitors as shown in figure 3. figure 3. external xtal with optional load capacitors 4.2. external clo ck input pin (clkin) the external clock input is used as a reference for gen erating synchronous clocks. the input frequency can be specified from 10 to 100 mhz including fractional fr equencies (e.g., 74.25 mhz x 10 00/1001). the clockbuilder utility automatically determine s the exact synthesis ratio to guarantee an ou tput frequency wit h 0 ppm error with respect to its reference. 4.3. output clocks (clk0?clk7) the si5350c is orderable as a 3-output (10-msop) or 8-output (24-qsop, 20-qfn) clock generator. output clocks clk0 to clk5 can be ordered with two clock frequencies (f1_x, f2_x) which are selectable with the optional frequency select pins (fs0/1). see ?4.4 .2. frequency select (fs_0, fs_1)? for more details on the operation of the frequency select pins. each output clock can select its reference for either of the plls. 4.3.1. output clock frequency outputs can be configured at any frequency from 8 khz up to 100 mhz. in addition, the device can generate any two non-integer related frequencies up to 125 mhz. 4.3.2. . spread spectrum spread spectrum can be enabled on any of the clock outputs that use pll_b as its reference. spread spectrum is useful for reducing electromagnetic interference (emi). e nabling spread spectrum on an output clock modulates its frequency, which effectively reduces the overall amplitude of its radiated energy. up to ?15 db reduction in emi is possible. the si5350c supports several levels of spread spectrum allowing the des igner to chose an ideal compromise xa xb optional internal load capacitors 6pf, 8pf, 10pf c l c l c l optional external load capacitors c l
si5350c rev. 0.2 11 between system performance and emi compliance. the am ount of spread is configurable within the following parameters: ? down spread: ?0.5 to ?2.5% modulation amplitude an optional spread spec trum enable pin (ssen) is conf igurable to enable or disable the spread spectrum feature. see ?4.4.1. spread spectrum enable (ssen)? for details. figure 4. available spread spectrum profiles 4.3.3. invert/non-invert by default, each of the output clocks are generated in ph ase (non-inverted) with respect to each other. an option to invert any of the clock outputs is also available. 4.3.4. output state when disabled there are up to three output enable pins configurable on the si5350c as described in ?4.4.5. loss of lock (lol)? . the output state when disabled for each of the outputs is configurable as one of the fo llowing: disable low, disable high, or disable in high-impedance. 4.3.5. powering down unused outputs unused clock outputs can be completely powered down to conserve power. 4.4. programmable cont rol pins (p0?p3) options up to four programmable control pins (p0-p3) are configur able allowing direct pin control of the following features: 4.4.1. spread spec trum enable (ssen) an optional control pin allows disabling the spread spec trum feature for all outputs that were configured with spread spectrum enab led. hold ssen low to disa ble spread spectrum. the ssen pin provides a convenient method of evaluating the effect of using spre ad spectrum clocks during emi compliance testing. 4.4.2. frequency select (fs_0, fs_1) the si5350c offers the option of configuring up to tw o frequencies per clock output (clk0-clk5) for either free- running or synchronous clocks. this is a useful feature for applications that need to support more than one free- running or synchronous clock rate on the same output. an example of this is shown in figure 5. the fs pins select which frequency is generated from the clock output. in th is example fs0 select the output frequency on clk0, and fs1 selects the fr equency on clk1. f c reduced amplitude and emi down spread spread amount - 0.5% to - 2.5% f c no spread spectrum center frequency amplitude
si5350c 12 rev. 0.2 figure 5. example of generating two clock frequencies from the same clock output up to two frequency select pins are available on the si 5350c. each of the frequency select pins can be linked to any of the clock outputs as shown in figure 6. for example, fs_0 can be linked to control clock frequency selection on clk0, clk3, and clk5; fs_1 can be used to control clock frequency selection on clk1, clk2, and clk4. any other combinat ion is also possible. the si5350c uses control circuitry to ensure that freque ncy changes are glitchless. th is ensures that the clock always completes its last cycle before starting a new clock cycle of a different frequency. figure 6. example configuration of a pin-controlled frequency select (fs) 4.4.3. output enable (oeb_0, oeb_1, oeb_2) up to three output enable pins (oeb_0/1/2) are available on the si5350c. similar to the fs pins, each oeb pin can be linked to any of the output clocks. in the exam ple shown in figure 7, oeb_0 is linked to control clk0, clk3, and clk5; oeb_1 is linked to c ontrol clk6 and clk7, and oeb_2 is linked to control clk1, clk2, clk4, and clk5. any other combination is also possible. if more than one oeb pin is linked to the same clk output, the pin forcing a disable state will be dominant. clock ou tputs are enabled when t he oeb pin is held low. the output enable control circuitry ensures glitchless operati on by starting the output clock cycle on the first leading edge after oeb is asserted (oeb = low). when oeb is rele ased (oeb = high), the clock is allowed to complete its full clock cycle before going into a disabled state. this is shown in figure 7. when disabled, the output state is configurable as disabled high, disabled low, or disabled in high-impedance. 74.25 mhz or 74.25 1.001 mhz 27 mhz xa xb clk0 fs0 si5350c free-running clock fs1 clkin 24.576 mhz or 22.5792 mhz clk1 synchronous clock video/audio processor free-running frequency fs0 bit level 0 1 74.25 mhz f1_0: f2_0: 74.25 1.001 mhz synchronous frequency fs1 bit level 0 1 24.576 mhz f1_1: f2_1: 22.5792 mhz 54mhz clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 fs_0 fs_1 fs_0 0 1 f1_0, f1_3, f1_5 f2_0, f2_3, f2_5 output frequency fs_1 0 1 f1_1, f1_2, f1_4 output frequency clkx frequency_a frequency_b full cycle completes before changing to a new frequency frequency_a new frequency starts at its leading edge glitchless frequency changes cannot be controlled by fs pins customizable fs control f2_1, f2_2, f2_4 multisynth 0 fs multisynth 1 fs multisynth 2 fs multisynth 3 fs multisynth 4 fs multisynth 5 fs
si5350c rev. 0.2 13 figure 7. example configuration of a pin-controlled output enable clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 oeb_0 oeb_1 oeb_0 0 1 clk enabled clk disabled output state oeb_2 oeb_1 0 1 clk enabled clk disabled output state oeb_2 0 1 clk enabled clk disabled output state clock continues until cycle is complete clkx oebx clock starts on the first leading edge glitchless output enable customizable oeb control oeb oeb oeb oeb oeb oeb oeb oeb
si5350c 14 rev. 0.2 4.4.4. power down (pdn) an optional power down control pin allows a full shutdown of the si5350c to minimize power consumption when its output clocks are not being used. the si535 0c is in normal operation when the pdn pin is held low and is in power down mode when held high. power consumption when the device is in power down mode is indicated in table 3 on page 4. 4.4.5. loss of lock (lol) a loss of lock pin (lol) is available to indicate the status of the synchronous clock outputs. the lol pin is set to a low state when the synchronous clock outputs are locked to the clock input (clkin). this is the normal operating state for the synchronous clocks. the lol pin will go high when the reference clock at the clkin input is removed or if its frequency deviates by more than 2000 ppm from its defined center frequency. in this case, the synchronous clocks will continue to free-run. an option to disable the synchronous out put clocks during an lol condition (lol pin = high) is available. this only affects the clock outputs that were designated as synchronous clock outputs. 4.5. design considerations the si5350c is a self-contained clock generator that requires very few exte rnal components. the following general guidelines are recommended to ensure optimum performance. 4.5.1. power supply decoupling/filtering the si5350c has built-in power supply filtering circuitry to help keep the number of external components to a minimum. all that is recommended is one 0.1 f decouplin g capacitor per power supply pin. this capacitor should be mounted as close to the vdd and vddo pins as possible without using vias. 4.5.2. power supply sequencing the vdd and vddox (i.e., vddo0, v ddo1, vddo2, vddo3) power supply pins have been separated to allow flexibility in output signal le vels. it is important that po wer is applied to all supply pins (vdd, vddox) at the same time. unused vddox pins should be tied to vdd. 4.5.3. external crystal the external crystal should be mounted as close to th e pins as possible using short pcb traces. the xa and xb traces should be kept away from other high-speed signal traces. see ?an5 51: crystal selection guide? for more details. 4.5.4. external crystal load capacitors the si5350c provides the option of using internal and exte rnal crystal load capacitors. if external load capacitors are used, they should be placed as close to the xa/xb pads as possible. see ?an551: crystal selection guide? for more details. 4.5.5. unused pins unused control pins (p0?p3) should be tied to gnd. unused clkin pin should be tied to gnd. unused xa/xb pins should be tied to gnd. unused output pins (clk0?clk7) should be left unconnected.
si5350c rev. 0.2 15 5. pin descriptio ns (20-qfn, 24-qsop) pin name pin number pin type function 20-qfn 24-qsop xa 1 6 i input pin for external xtal xb 2 7 i input pin for external xtal clkin 6 12 i external reference clock input clk0 13 21 o output clock 0 clk1 12 20 o output clock 1 clk2 9 15 o output clock 2 clk3 8 14 o output clock 3 clk4 19 3 o output clock 4 clk5 17 1 o output clock 5 clk6 16 24 o output clock 6 clk7 15 23 o output clock 7 p0 3 9 i user configurable input pin 0. see 4.5.5 p1 4 10 i user configurable input pin 1. see 4.5.5 p2 5 11 i user configurable input pin 2. see 4.5.5 p3 7 13 i user configurable input pin 3. see 4.5.5 vdd 20 4 p core voltage supply pin. see 4.5.2 vddoa 11 18 p output voltage supply pin for clk0 and clk1. see 4.5.2 vddob 10 16 p output voltage supply pin for clk2 and clk3. see 4.5.2 vddoc 18 2 p output voltage supply pin for clk4 and clk5. see 4.5.2 vddod 14 22 p output voltage supply pin for clk6 and clk7. see 4.5.2 gnd center pad 5, 8, 17, 19 p ground note: pin types: i = input, o = output, p = power 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 gnd pad xa xb p0 p1 p2 p3 clk3 clk2 vddob clkin si5350c 20-qfn top view clk6 clk5 vddoc clk4 vdd vddoa clk1 clk0 vddod clk7 2 1 4 3 6 5 8 7 10 9 12 11 23 24 21 22 19 20 17 18 15 16 13 14 si5350c 24-qsop top view clk7 clk6 clk0 vdd0d gnd clk1 gnd vddoa clk2 vdd0b p3 clk3 vddoc clk5 vdd clk4 xa gnd gnd xb p1 p0 clkin p2
si5350c 16 rev. 0.2 6. pin descriptions (10-msop) pin name pin number pin type function 10-msop xa 2 i input pin for external xtal xb 3 i input pin for external xtal clkin 5 i external reference clock input clk0 10 o output clock 0 clk1 9 o output clock 1 clk2 6 o output clock 2 p0 4 i user configurable input pin 0 . see 4.5.5 vdd 1 p core voltage supply pin . see 4.5.2 vddo 7 p output voltage supply pin for clk0, clk1, and clk2 . see 4.5.2 gnd 8 p ground note: pin types: i = input, o = output, p = power xa vdd p0 xb 2 1 4 3 clk1 clk0 vddo gnd 9 10 7 8 clkin 5 clk2 6 si5350c 10-msop top view
si5350c rev. 0.2 17 7. package outline (24-pin qsop) table 10. 24-qsop package dimensions dimension min nom max a??1.75 a1 0.10 ? 0.25 b 0.19 ? 0.30 c 0.15 ? 0.25 d 8.558.658.75 e 6.00 bsc e1 3.81 3.90 3.99 e 0.635 bsc l 0.40 ? 1.27 l2 0.25 bsc q0?8 aaa 0.10 bbb 0.17 ccc 0.10 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation c 4. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components.
si5350c 18 rev. 0.2 8. package outline (20-pin qfn) table 11. package dimensions dimension min nom max a 0.800.850.90 a1 0.00 0.02 0.05 b 0.180.250.30 d 4.00 bsc d2 2.65 2.70 2.75 e 0.50 bsc e 4.00 bsc e2 2.65 2.70 2.75 l 0.300.400.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.10 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components. ?
si5350c rev. 0.2 19 8.1. package outline (10-pin msop) table 12. 24-qsop package dimensions dimension min nom max a??1.10 a1 0.00 ? 0.15 a2 0.75 0.85 0.95 b 0.17 ? 0.33 c 0.08 ? 0.23 d 3.00 bsc e 4.90 bsc e1 3.00 bsc e 0.50 bsc l 0.400.600.80 l2 0.25 bsc q0?8 aaa ? ? 0.20 bbb ? ? 0.25 ccc ? ? 0.10 ddd ? ? 0.08 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation c 4. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components. ?
si5350c 20 rev. 0.2 9. ordering information factory-programmed si5350c devices can be requested using the clock builder web-based utility available at: www.silabs.com/clockbuilder . a unique part number is assigned to each custom configuration as indicated in figure 8. figure 8. custom clock part numbers a development kit containing clockbuilder desktop software and hardware enable easy field programming of blank si5350c devices for instances when rapid prototyping is required. note that the si5350c can only be field- programmed using the development kit. in addition to field programming, this development kit supports simplified device evaluation of any si5350c devi ce. the orderable part numbers for the development kits and blank si5350c devices to be used for field programming are provided in figure 9 and figure 10, respectively. figure 9. development kit part numbers figure 10. blank device part numbers si5350c axxxxx xx gt - 10-msop gm - 20-qfn gu - 24-qsop a = product revision a xxxxx = unique custom code. a five character code will be assigned for each unique custom configuration si535x evb xxxxxx evb = device and field programming kit xxxxxx = 20qfn 24qsop si5350c a xx gt - 10-msop gm - 20-qfn gu ? 24-qsop a = product revision a ? blank device
si5350c rev. 0.2 21 n otes :
si5350c 22 rev. 0.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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